Description
The AI4HPCC workshop explores the rapidly growing intersection between artificial intelligence (AI) and high-performance compiler construction, focusing on how large language models (LLMs), reinforcement learning, and other AI-driven methods can revolutionize the way we design, optimize, and deploy compilers for modern and emerging computing architectures, in both academic research and industrial practice.
As high-performance computing systems evolve to include heterogeneous processors, accelerators, advanced memory hierarchies, and novel interconnects, compiler design faces unprecedented complexity. Traditional heuristic-based optimization approaches struggle to keep pace with the increasing diversity of architectures and programming models. AI4HPCC aims to address these challenges by fostering discussion on AI-enhanced techniques that can automate, generalize, and accelerate the compiler optimization pipeline — from code analysis and transformation to performance modeling and autotuning.
Important Dates
📤 Proposals should be submitted to: EasyChair
Call for Papers
We invite researchers from academia and industry to present their work on the following topics (including but not limited to):
- Machine learning-based compiler optimization and code generation
- AI-driven performance modeling, prediction, and optimization
- Large language models for compiler development
- Integration of AI-enhanced compilers with HPC runtimes and programming models
- Benchmarks, datasets, and tooling for AI-based compiler research
The workshop will publish its proceedings with the ICS 2026 conference. Authors must follow the same formatting guidelines as main conference papers (ACM template, \documentclass[sigconf]{acmart} in LaTeX). Submitted manuscripts may not exceed eight (8) pages in length for regular papers and at least (4) pages for short papers, excluding references.
Agenda
- To be confirmed
Organizing Committee
Workshop 2026 Organizers
Huimin Cui is a Professor at ICT, CAS. Her research focuses on compiler optimizations for heterogeneous architectures (GPU, NPU, DPU, and other ASICs), particularly for AI and big data workloads. She also works on software–hardware co-design enabled by compiler analysis.
Zheng Wang is Professor of Intelligent Software Technology at the University of Leeds and a Royal Society Industry Fellow. He is known for his work in combining machine learning and compiler-based code analysis techniques.
Jiacheng Zhao is an Associate Professor at ICT, CAS. His research focuses on building next-gen compiler infrastructure for domain specific accelerators, e.g. GPUs, AI Chips and network processors.
Fang Lyu is a senior engineer at ICT, CAS. Her research focuses on developing compilation optimization systems for high-performance RISC-V processors, architecture-oriented performance analysis, and advanced compiler optimizations.
Ying Liu is a senior engineer at ICT, CAS. Her main research interests include compiler optimizations for heterogeneous architectures, compiler optimization and parallel programming.
Chenxi Wang is an associate professor at ICT, CAS. His research interest is to build hard-core systems, managed runtime and big data systems for emerging hardware, such as GPUs and resource-disaggregated datacenters.
Workshop 2026 Program Committee
- Huimin Cui, ICT, CAS, China
- Zheng Wang, University of Leeds, UK
- Jiacheng Zhao, ICT, CAS, China
- Fang Lyu, ICT, CAS, China
- Ying Liu, ICT, CAS, China
- Chenxi Wang, ICT, CAS, China
- Guangli Li, ICT, CAS, China
- Chunwei Xia, University of Leeds, UK
- Lei Qiu, ICT, CAS, China
Contact
For any question(s) related to AI4HPCC 2026, please contact the Chair Huimin Cui.