Description
The AI4HPCC workshop explores the rapidly growing intersection between artificial intelligence (AI) and high-performance compiler construction, focusing on how large language models (LLMs), reinforcement learning, and other AI-driven methods can revolutionize the way we design, optimize, and deploy compilers for modern and emerging computing architectures, in both academic research and industrial practice.
As high-performance computing systems evolve to include heterogeneous processors, accelerators, advanced memory hierarchies, and novel interconnects, compiler design faces unprecedented complexity. Traditional heuristic-based optimization approaches struggle to keep pace with the increasing diversity of architectures and programming models. AI4HPCC aims to address these challenges by fostering discussion on AI-enhanced techniques that can automate, generalize, and accelerate the compiler optimization pipeline — from code analysis and transformation to performance modeling and autotuning.
Important Dates
📤 Proposals should be submitted to: EasyChair
Call for Papers
We invite researchers from academia and industry to present their work on the following topics (including but not limited to):
- Machine learning-based compiler optimization and code generation
- AI-driven performance modeling, prediction, and optimization
- Large language models for compiler development
- Integration of AI-enhanced compilers with HPC runtimes and programming models
- AI for quantum compilation and optimization
- Benchmarks, datasets, and tooling for AI-based compiler research
The workshop will publish its proceedings with the ICS 2026 conference. Authors must follow the same formatting guidelines as main conference papers (ACM template, \documentclass[sigconf]{acmart} in LaTeX). Submitted manuscripts may not exceed eight pages in length for regular papers and 5 pages for short papers, excluding references.
Agenda
| Time | Title | Speaker | Affiliation |
|---|---|---|---|
| 09:00 - 09:10 (10 min) | Welcome and Opening Remarks | HuiminCui & Zheng Wang | |
| 09:10 - 09:30 (20 min) | From Naive CUDA to Triton: A Systematic Evaluation of AI-Era HPC Operator Development | Chunwei Xia | University of Leeds |
| 09:30 - 09:50 (20 min) | FHECrafter: A Multi-Agent Framework for Automated Fully Homomorphic Encrypted Tensor Program Generation | Qiuchu Yu | University of Chinese Academy of Sciences |
| 09:50 - 10:10 (20 min) | Towards fully automated compiler backend generation with multi-agent systems: how far are we? (Online) | Ming Zhong | The Chinese University of Hong Kong |
| 10:10 - 10:30 (20 min) | Agent-Agnostic End-to-End C/C++ Application Performance Optimization | Chunwei Xia | University of Leeds |
| 10:30 - 11:00 (20 min) | Coffee Break | ||
| 11:00 - 11:20 (20 min) | Compiler-ASR: Bridging the IR-to-Assembly Gap for Compiler Optimization via Architecture-Specific Reward (Online) | Kai Zhang | Beijing University of Posts and Telecommunications |
| 11:20 - 11:40 (20 min) | Augmenting LLM Code Translation with Compiler Analysis for C to Triton Kernel Generation | Xiao Qin | University of Leeds |
| 11:40 - 12:00 (20 min) | CoLo: Correcting LLM-Generated IR with Precise Error Location (Online) | Jiahao Chen | China West Normal University |
| 12:30 - 13:30 (60 min) | Lunch | - | - |
| 13:30 - 13:50 (20 min) | Enhance Performance Tuning via LLM-guided Search Templates | yassine marzouki | University of Leeds |
| 13:50 - 14:10 (20 min) | RV-IR: An MLIR-Based Architecture-Aware Intermediate Representation for Heterogeneous RISC-V AI Acceleration (Online) | Zexin Jian | University of Chinese Academy of Sciences |
| 14:10 - 14:30 (20 min) | CompLift:LLM-Assisted Compiler API Migration with Semantic Alignment (Online) | Yang Yang | China West Normal University |
| 14:30 - 15:00 (30 min) | Closing Remarks | HuiminCui & Zheng Wang |
Organizing Committee
Workshop 2026 Organizers
Huimin Cui is a Professor at ICT, CAS. Her research focuses on compiler optimizations for heterogeneous architectures (GPU, NPU, DPU, and other ASICs), particularly for AI and big data workloads. She also works on software–hardware co-design enabled by compiler analysis.
Zheng Wang is Professor of Intelligent Software Technology at the University of Leeds and a Royal Society Industry Fellow. He is known for his work in combining machine learning and compiler-based code analysis techniques.
Jiacheng Zhao is an Associate Professor at ICT, CAS. His research focuses on building next-gen compiler infrastructure for domain specific accelerators, e.g. GPUs, AI Chips and network processors.
Fang Lyu is a senior engineer at ICT, CAS. Her research focuses on developing compilation optimization systems for high-performance RISC-V processors, architecture-oriented performance analysis, and advanced compiler optimizations.
Ying Liu is a senior engineer at ICT, CAS. Her main research interests include compiler optimizations for heterogeneous architectures, compiler optimization and parallel programming.
Chenxi Wang is an associate professor at ICT, CAS. His research interest is to build hard-core systems, managed runtime and big data systems for emerging hardware, such as GPUs and resource-disaggregated datacenters.
Workshop 2026 Program Committee
- Huimin Cui (Chair), ICT, CAS, China
- Zheng Wang (Chair), University of Leeds, UK
- Guangli Li, ICT, CAS, China
- Chunwei Xia, University of Leeds, UK
- Xueying Wang, Beijing University of Posts and Telecommunications, China
- Zhiding Liang, The Chinese University of Hong Kong, China
- Guancheng Wang, University of Limerick, Ireland
- Yuan Wen, University of Aberdeen, UK
- Vasilios Kelefouras, University of Plymouth, UK
- Lei Qiu, ICT, CAS, China
Contact
For any question(s) related to AI4HPCC 2026, please contact the Chair Huimin Cui.